The present inventors have made the following search and study. More specifically, currently, a great many of radio communication systems exist in the world. For this reason, a terminal usable a plurality of systems has been required. To give an example, there are a GSM (Global System for Mobile communications) and a DCS 1800 (Digital Cellular system 1800). These systems have similar modulation system although an operation frequency band is different.
A PLL circuit has been described in “Phase lock Techniques” (ISBN 0-471-04294-3) section 10.3 published by John Wiley & Sons Company. The PLL circuit converts an IF signal into an RF signal in one operation frequency band. Although the technique shown in FIG. 9 is not known, it shows one example in which the PLL circuit studied by the present inventors is constructed so as to be usable in a plurality of operation frequency bands.
The above PLL circuit comprises a phase comparator 41, a mixer 2, n (n is two or more natural number) low-pass filters (LPF) 42-1 to 42-n, n voltage control oscillators (VCO) 4-1 to 4-n, n couplers 43-1 to 43-n, and a control circuit 6 for controlling the on/off of these VCOs 4-1 to 4-n.
Two signals are inputted to the phase comparator 41. A first input signal is a reference signal IF, and a second input signal is an output signal from the mixer 2. The reference IF signal and the output signal from the mixer 2 is compared in its phase, and then, a signal is outputted in proportional to a phase difference. An output signal from the phase comparator 41 is outputted to the LPFs 42-1 to 42-n so that unnecessary noise is eliminated, and thereafter, is inputted to the VCOs 4-1 to 4-n. The control circuit 6 operates one VCO of the above n VCOs in accordance with a desired operation frequency band, and then, other VCOs are controlled to an off state so as not to output a signal. The output frequencies of the VCOs 4-1 to 4-n are individually fVCO1 to fVCOn, and are inputted to the couplers 43-1 to 43-n. In the coupler, the input signal is outputted after being branched into two. A first output of the coupler is an output signal of the PLL circuit, and a second output thereof is inputted to the mixer 2. Two signals are inputted to the mixer 2, and a first input signal of the mixer is the second output signal of the couplers 43-1 to 43-n. A local oscillator signal RF-LO having a frequency fLO is inputted to the second input of the mixer 2. An output frequency of the mixer 2 is an absolute value of difference between two input frequencies, that is, |fLO−fVCOn|. The output signal of the mixer 2 is the second input signal of the phase comparator 41. Now, if the VCO 4-n is operated, in a state that the PLL circuit is locked, two input frequencies of the phase comparator 41 become equal; for this reason, the input frequency is fIF=|fLO−fVCOn|. Therefore, an output frequency fVCOn of the VCO 4-n is obtained from |fLO−fIF|. Namely, the reference signal frequency fIF to the PLL circuit is converted into fVCOn=|fLO−fIF|.
An operation of the PLL circuit will be analyzed below using a linear model. In this case, the VCO 4-n is selected as the VCO. A phase difference conversion gain of the phase comparator 41 is set as Kd, and a sensitivity of the selected VCO 4-n is set as Kv. Moreover, a lag lead filter is used as the LPF 42-n. Thus, a transfer function F(s) of the LPF 42-n is obtained from the following equation (1).
                              F          ⁡                      (            s            )                          =                              1            +                          s              ·              C              ·              R2                                            1            +                          s              ·              C              ·                              (                                  R1                  +                  R2                                )                                                                        (        1        )            
Moreover, an open loop transfer function Ho of the PLL circuit is obtained from the following equation (2).Ho=Kd·Kv·F(s)  (2)
The pole ωp and zero ωz of the above open loop transfer function Ho are obtained from the following equations (3) and (4), respectively.
                              ω          ⁢                                          ⁢          p                =                  1                      C            ·                          (                              R1                +                R2                            )                                                          (        3        )                                          ω          ⁢                                          ⁢          z                =                  1                      C            ·            R2                                              (        4        )            
When the above ωp and ωz are both smaller than a loop band K of the PLL circuit, the loop band K is obtained from the following equation (5).
                    K        =                  Kd          ·          Kv          ·                      R2                          R1              +              R2                                                          (        5        )            
Therefore, the above loop band K is determined by the aforesaid Kd, Kv, and the transfer function F(s) of the LPF 42-n. The above Kd is a constant; however, in general, the above Kv is different depending upon an operation frequency band. Thus, the characteristics of the LPFs 42-1 to 42-n must be designed in accordance with the above Kv.
By the way, the present inventors have made the study of the aforesaid PLL circuit; as a result, they have found the following matter. More specifically, the aforesaid PLL circuit requires n LPFs for using the plurality of operation frequency bands. In general, the phase comparator is built in an IC; on the other hand, the LPF is mounted outside the IC. For this reason, the number of components mounted outside increases; as a result, a problem arises such that terminal mounting becomes complicate, and the mounting area increases. Further, in the case of using n LPFs, the IC requires n pins corresponding to n LPFs; for this reason, a problem arises such that the number of pins increases. Furthermore, a design must be made with respect to each of n LPFs; for this reason, a problem arises such that the design of LPF becomes complicate.
It is, therefore, an object of the present invention to provide a PLL circuit, which reduces the number of n LPFs required in the above PLL circuit to only one LPF, and thereby, can reduce a mounting area and the number of pins, and can simplify a design, and to provide a radio communication terminal apparatus using the PLL circuit.
The above, other objects and novel features of the present invention will be more apparently understood from the description of this specification and the accompanying drawings.